0.18μm 1.8V 10bit 100MS/s CMOS电流舵D/A IP设计与验证  

Design and Verification of 0.18 μm 1.8 V 10 bit 100 MS/s CMOS Current-Steering D/A IP

作　　者：邵博闻 刘芸 俞慧月 易伟 张辉 

机构地区：[1]上海硅知识产权交易中心,上海200030

出　　处：《半导体技术》2010年第6期614-617,共4页Semiconductor Technology

摘　　要：基于GSMC 0.18μm CMOS工艺,采用曲率补偿带隙参考电压源和中心对称Q2随机游动对策拓扑方式的NMOS电流源阵列版图布局,实现了一种10 bit 100 MS/s分段温度计译码CMOS电流舵D/A转换器。当电源电压为1.8 V时,D/A转换器的功耗为10 mW,微分非线性误差和积分非线性误差分别为1 LSB和0.5 LSB。在取样速率为100 MS/s,输出频率为5 MHz条件下,SFDR为70 dB,10 bit D/A转换器的有效版图面积为0.2 mm2,符合SOC的嵌入式设计要求。Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q2 random walk NMOS current source layout routing method,a 1.8 V 10 bit 100 MS/s CMOS current-steering D/A converter was implemented with GSMC 0.18 μm CMOS process.The total consumption is only 10 mW from single 1.8 V power supply,and the integral and differential nonlinearity errors are measured to be less than 1 LSB and 0.5 LSB,respectively.When the output signal frequency is 5 MHz at 100 MS/s sampling rate,the SFDR is measured to be 70 dB.The die area is about 0.2 mm2.

关 键 词：电流舵DAC 低功耗 电流源阵列 匹配误差 带隙基准电压源 

分 类 号：TN386.1[电子电信—物理电子学]