DC-DC变换器中CMOS电荷泵锁相环的设计  

Design of CMOS Charge Pump Phase Locked Loop for DC-DC Converter

作　　者：黄可[1] 冯全源[1] 

机构地区：[1]西南交通大学微电子研究所,成都610031

出　　处：《微电子学》2010年第3期339-342,共4页Microelectronics

基　　金：国家自然科学基金-中物院联合基金资助项目(10876029)

摘　　要：针对电荷泵锁相环的抖动问题,对CMOS电荷泵锁相环的压控振荡器电路进行改进;设计了一种采用增益补偿技术的压控振荡器,实现了可用于DC-DC变换器中与外部时钟同步的电荷泵锁相环。电路设计基于TSMC 0.18μm CMOS工艺,采用HSPICE软件仿真验证。仿真结果表明,在3.3 V电源电压-、40℃-85℃温度范围内,该电荷泵锁相环能够与外部时钟同步于1.5-3.5 MHz的频率范围,锁定时间小于72μs,功耗小于1.3 mW。To solve the problem of jitter in charge pump phase locked loop（CPPLL）,an improved voltage controlled oscillator was designed using gain compensation technique.The CPPLL could be used in DC-DC converter to synchronize with external clock signal.Based on TSMC＇s 0.18 μm CMOS process,the circuit was verified with HSPICE.Simulation results showed that,at 3.3 V supply voltage and in the temperature range from-40 ℃ to 85 ℃,the proposed CPPLL could synchronize with external clock signal in 1.5-3.5 MHz frequency range with lock-ing time below 72 μs and power dissipation less than 1.3 mW.

关 键 词：电荷泵锁相环 压控振荡器 DC-DC变换器 

分 类 号：TN432[电子电信—微电子学与固体电子学]