适用于谐振时钟的CMOS触发器研究  

Study on CMOS Flip-Flop for Sinusoidal-Clock

作　　者：叶茂[1] 刘海南[1] 周玉梅[1] 

机构地区：[1]中国科学院微电子研究所专用集成电路与系统实验室,北京100029

出　　处：《微电子学》2010年第3期382-386,共5页Microelectronics

基　　金：国家自然科学基金资助项目(60676015)

摘　　要：构建的两种适用于谐振时钟的CMOS触发器结构:SAER(Sense Amplifier Energy Re-covery)和SDER(Static Differential Energy Recovery),克服了传统触发器在谐振时钟触发下短路功耗大的问题,适用于对时钟网络实现能量回收与节省的系统。在SMIC 0.13μm工艺下进行功耗和时序参数仿真,对比应用在同样谐振时钟下的传统主从结构触发器MSDFF(Master-Slave DFlip-flop)和高性能触发器HLFF(Hybrid Latch Flip-flop),SAER在测试的频率范围内保证高性能时序参数的同时,实现了三分之一以上的功耗节省。Two sinusoidal-clock-based CMOS flip-flops（SAER and SDER） were presented,which overcame the problem of large short-circuit power in traditional sinusoidal clock flip-flops,and is suitable for systems with energy recovery clock tree.The circuits were simulated based on SMIC＇s 0.13 μm process,and a comparison was made with other two types of traditional flip-flop（MSDFF and HLFF） driven by sinusoidal clock.Results showed that SAER had a maximum power saving by 1/3 at 300 MHz,while maintaining high performance.

关 键 词：低功耗 能量回收技术 谐振时钟 SAER SDER 

分 类 号：TN432[电子电信—微电子学与固体电子学]