基于32位SPARC处理器的JTAG仿真器设计与实现  

Design and Implementation of 32-Bit SPARC Processor-Based JTAG Emulator

作　　者：张晓静[1] 华更新[1] 刘超伟[1] 乔磊[1] 

机构地区：[1]北京控制工程研究所,北京100190

出　　处：《空间控制技术与应用》2010年第3期59-62,共4页Aerospace Control and Application

摘　　要：在研究IEEE1149.1标准和JTAG调试原理的基础上,以SPARC处理器内嵌调试体系结构为核心,设计实现一种JTAG仿真器.JTAG仿真器通过以太网和串口与上位机通信,利用FPGA发送JTAG协议时序完成用户调试任务.该系统设计可扩展性好,成本低,且JTAG数据发送速率可达到8Mbit/s、性价比高.经测试,该系统能稳定、可靠工作.on the basis of research on IEEE Std. 1149.1 and debugging principle of JTAG, a JTAG emulator using the embedded debugging architecture of 32-bit SPARC processor as a hard core is designed and imple- mented. The emulator user Ethernet and serial interfaces for communicating with PC and FPGA for sending the JTAG protocol timing sequence to accomplish de- bugging task to uses. The system design has better ex- tendibility, its data transfer rate can reach 8M bit/s, and can achieve high performance/cost ratio. Experiment results show that the system can be able to operate steadily and reliably.

关 键 词：JTAG 仿真器 嵌入式调试 SPARC处理器 

分 类 号：TP337[自动化与计算机技术—计算机系统结构]