100G以太网自同步并行扰码算法实现  

Self-synchronization Scrambling Algorithm and Its Implementation in 100G Ethernet

作　　者：张立鹏[1] 朱清新[1] 青华平[2] 

机构地区：[1]电子科技大学计算机科学与工程学院,四川成都610054 [2]华为技术有限公司成都研究所,四川成都610041

出　　处：《通信技术》2010年第5期135-137,142,共4页Communications Technology

摘　　要：扰码是在数字传输系统中,对于数字信息进行随机化处理的一种技术,被广泛应用于通信各个领域。首先介绍了扰码和自同步扰码的基本原理,通过对扰码原理的分析,实现了一种任意特征多项式、任意N位并行自同步扰码算法,并可演算得到任意特征多项式、任意N位并行帧同步扰码算法。该方法采用递推的方法直接得出N个时钟周期后编码器的状态值与当前编码器状态值之间的逻辑关系。其逻辑运算速度快且实现简单,十分有利于硬件实现。然后研究了基于802.3ba未来100G以太网中640bits自同步扰码算法的FPGA实现,给出了组合逻辑实现和时序逻辑实现两种方案,并对两种方案进行了对比分析,最后给出了640bits并行扰码器实现资源需求分析。In telecommunications,the scrambling is a technique that transposes or inverts digital signals,which is widely used in various areas of communications.First,the theory of scrambling and self-synchronization scrambling is described.Based on this theory,a N-bit parallel self-synchronization scrambling algorithm is discussed in this paper,and it can achieve a N-bit parallel frame synchronous scrambling.This algorithm uses a recursive method to calculate the logic relationship of the scrambler,and its logic operation is quite fast,and easy in implementation by handware.Then the 640-bit parallel self-synchronization scrambling algorithm in 100G Ethernet is implemented on FPGA.Then the two schemes of combinatorial logic method and temporal Logic method are given,and their differences are compared.Finally,the analysis on resource demand of 640-bit parallel scrambler is provided.

关 键 词：扰码 自同步扰码 帧同步扰码 100G以太网 FPGA 

分 类 号：TN915.11[电子电信—通信与信息系统]