A low-cost compact AES architecture for wireless sensor network  

作　　者：易立华 Zou Xuecheng Liu Zhenglin Dan Yongping Zou Wanghui 

机构地区：[1]Department of Electronic Science ＆ Technology, Huazhong University of Science ＆ Technology, Wuhan 430074, P.R. China

出　　处：《High Technology Letters》2010年第2期184-188,共5页高技术通讯（英文版）

摘　　要：The implementation of small size cryptography algorithm is a critical problem for wireless sensor network. A low cost compact intellectual property （IP） core of the entire advanced encryption standard （AES） algorithm for wireless sensor network is presented in this paper. A compact encryption and decryption system using only four sharing S-Boxes is obtained, employing sharing between the encryption and decryption processes. Our design proposes use of composite field data path for the SubBytes and InvSubBytes transformations. With an implementation of the AES block cipher with Virtex Ⅱ Pro FPGA using0.13μm and 90nm process technology, our area optimized consumes 16.8k equivalent gates. The speed of this implementation is also reduced to 0.45Gbits/s. Compared with previous implementations, our design achieves significant low-cost area with acceptable throughput.

关 键 词：advanced encryption standard （AES） S-Boxes key expansion implement 

分 类 号：TN405[电子电信—微电子学与固体电子学] TP212[自动化与计算机技术—检测技术与自动化装置]