Low power and high speed explicit-pulsed double-edge triggered level converting flip-flop  

作　　者：戴燕云 Shen Jizhong 

机构地区：[1]Department of Information Science and Electronics Engineering, Zhejiang University, Hangzhou 310027, P.R. China [2]Faculty of Information and Electronics, Zhejiang Sci-Tech University, Hangzhou 310018, P.R. China

出　　处：《High Technology Letters》2010年第2期204-209,共6页高技术通讯（英文版）

基　　金：Supported by the National Natural Science Foundation of China （No.60503027） Acknowledgements： The authors are grateful to Prof. Zhao PeiYi of Chapman University, Orange, USA, for beneficial discussions.

摘　　要：Variable supply voltage-clustered voltage scaling （VS-CVS） scheme can be very effective in reducing power consumption of CMOS circuits without degrading system performance. Level converting flip-flops （LCFFs） are key elements in the CVS scheme. In this paper, a new explicit-pulsed double-edge triggered level converting flip-flop （nEP-DET-LCFF） is proposed, which employs double-edge triggering technique, dynamic structure, explicit pulse generator, conditional discharge technique and proper arrangement of stacked nMOS transistors to efficiently perform latching and level converting functions simultaneously. The proposed nEP-DET-LCFF combines merits of both conventional explicit-LCFFs and implicit-LCFFs. Simulation shows the proposed nEP-DET-LCFF has improvement of 19.2% -46% in delay, and 19.4% - 52.9% in power-delay product （PDP） as compared with the published LCFFs.

关 键 词：level converter FLIP-FLOP low power variable supply voltage 

分 类 号：TN782[电子电信—电路与系统] U292.91[交通运输工程—交通运输规划与管理]