基于FPGA的信道化接收机  

Channelized receiver based on FPGA

作　　者：侯碧波[1] 何子述[1] 李会勇[1] 

机构地区：[1]电子科技大学电子工程学院,四川成都611731

出　　处：《电子设计工程》2010年第7期164-166,共3页Electronic Design Engineering

基　　金：电子科学技术研究院预研基金项目(9140A07011609DZ0216)

摘　　要：针对宽带阵列侦收系统,设计一种基于FPGA的信道化接收机实现方案,并对各模块具体的实现进行了分析、设计,特别是基于FPGA的信道化模块。整个系统具有子信道频带窄、利于对信号进行精细化处理、功耗低、体积小、成本低、操作灵活以及易于扩展等特点。硬件系统测试结果验证了系统设计的有效性和可行性。This paper proposed a method of realizing the channelized receiver based on FPGA for wideband array intercepting system. The design and realization of each module,especially the channelized module, are analyzed in detail. The system designed several advantages ,such as having narrowband sub-channel, propitious to process signal subtly,low power dissipation, small volume, low cost, flexible for manipulating, easy for expanding, and so on. The hardware test results show the validity, and feasibility of our system design.

关 键 词：信道化接收机 可编程门阵列 多相滤波 EP2S60 AD6645 

分 类 号：TN971[电子电信—信号与信息处理]