A dual VCDL DLL based gate driver for zero-voltage-switching DC-DC converter  

作　　者：田鑫 刘祥昕 李文宏 

机构地区：[1]State Key Laboratory of ASIC & System,Fudan University

出　　处：《Journal of Semiconductors》2010年第7期137-143,共7页半导体学报（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(No.60676013).

摘　　要：This paper presents a dual voltage-controlled-delay-line（VCDL） delay-lock-loop（DLL） based gate driver for a zero-voltage-switching（ZVS） DC-DC converter.Using the delay difference of two VCDLs for the dead time control,the dual VCDL DLL is able to implement ZVS control with high accuracy while keeping good linearity performance of the DLL and low power consumption.The design is implemented in the CSM 2P4M 0.35μm CMOS process.The measurement results indicate that an efficiency improvement of 2%-4%is achieved over the load current range from 100 to 600 mA at 4 MHz switching frequency with 3.3 V input and 1.3 V output voltage.This paper presents a dual voltage-controlled-delay-line（VCDL） delay-lock-loop（DLL） based gate driver for a zero-voltage-switching（ZVS） DC-DC converter.Using the delay difference of two VCDLs for the dead time control,the dual VCDL DLL is able to implement ZVS control with high accuracy while keeping good linearity performance of the DLL and low power consumption.The design is implemented in the CSM 2P4M 0.35μm CMOS process.The measurement results indicate that an efficiency improvement of 2%-4%is achieved over the load current range from 100 to 600 mA at 4 MHz switching frequency with 3.3 V input and 1.3 V output voltage.

关 键 词：voltage-control-delay-line delay-lock-loop delay-unit ZERO-VOLTAGE-SWITCHING pseudo-current-control-inverter 

分 类 号：TM46[电气工程—电器]