基于FPGA的宽带数字接收机变带宽数字下变频器设计  

An FPGA implementation of variable-bandwidth digital down-converter in wideband digital receiver

作　　者：王晓[1] 夏威[1] 韩春林[1] 

机构地区：[1]电子科技大学电子工程学院,四川成都611731

出　　处：《电子技术应用》2010年第7期27-30,共4页Application of Electronic Technique

摘　　要：基于FPGA芯片Stratix II EP2S60F672C4设计了一个适用于宽带数字接收机的带宽可变的数字下变频器(VB-DDC)。该VB-DDC结合传统数字下变频结构与多相滤波结构的优点,实现了对输入中频信号的高效高速处理,同时可以在较大范围内对信号处理带宽灵活配置。硬件调试结果验证了本设计的有效性。Digital down-converter is an important part of wideband digital receivers. The variable-bandwidth digital down-converter （VB-DDC）,which is suitable for wideband digital receiver, is implemented in FPGA chip Stratix II EP2S60F672C4. The VB- DDC combines the advantages of traditional digital down-conversion architectures and poly-phase filter architectures, realizes effi- cient high-speed processing for input IF signal, and could configure the bandwidth of signal processing flexibly in a large range. Hardware test result shows the effectiveness of this design.

关 键 词：带宽可变 DDC 多相滤波 FPGA 

分 类 号：TN911.72[电子电信—通信与信息系统]