基于FPGA的τ因子内插滤波器设计与仿真  

Design and Simulation of Interpolator of τ Factor Based on FPGA

作　　者：丁红[1] 王庆东[2] 

机构地区：[1]上海第二工业大学计算机与信息学院,上海201209 [2]华中科技大学计算机科学与技术学院外存储系统国家专业实验室,武汉430074

出　　处：《计算机工程》2010年第14期206-208,共3页Computer Engineering

基　　金：国家自然科学基金资助项目(60303031)

摘　　要：针对传统的由锁相环构成的伺服时钟恢复电路噪声干扰大、锁定时间长的问题,在线性插值时钟恢复的基础上进行改进,提出基于τ因子的内插时钟模型,并推导出τ因子内插滤波器系数算法,设计内插滤波器的FPGA实现方案并进行仿真。实验结果证明,采用τ因子内插滤波器可以获得更好的谐波频谱,解决了传统硬盘伺服时钟恢复电路的噪声问题。This paper proposes an interpolation timing recovery model based on τ factor on the basis of improvement in linear interpolation clock recovery model,because traditional servo phase-locked loop timing recovery circuit has the problem of noise interference and long time lock.It conducts the algorithm of interpolator coefficient based on τ factor,researches and simulates the implementation of interpolator by FPGA.Experimental results show that the interpolated timing recovery model based on τ factor can obtain better harmonic frequency and solves the noise problem of traditional harddisk servo timing recovery circuit.

关 键 词：内插滤波器 滤波系数算法 τ因子 谐波频谱 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]