基于动态局部重配置的FPGA抗辐射模拟  

Radioresistance Emulation of FPGA Based on Dynamic Partial Reconfiguration

作　　者：刘智斌[1] 王伶俐[1] 周学功[1] 童家榕[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《计算机工程》2010年第14期218-220,226,共4页Computer Engineering

基　　金：国家自然科学基金资助面上项目(60676020);上海市浦江人才计划与上海市科委联合基金资助项目(08706200101)

摘　　要：提出一种与具体硬件结构无关、基于权重的错误注入模型,用于准确模拟基于SRAM的现场可编程门阵列抗辐射性能。提出基于JTAG边界扫描技术和动态局部重配置的错误注入模拟平台。实验结果证明,由该软件模型和硬件平台组成的错误注入系统具有良好通用性,能更准确、高效地进行模拟,且成本较低。This paper presents a hardware structure-independent weight-based fault injection model for accurate emulation of the radioresistance in the SRAM-based FPGA.Fault injection emulation platform based on Joint Test Action Group（JTAG） boundary scan and dynamic partial reconfiguration is proposed.Experimental results show that fault injection system composed of the software model and the hardware platform has high universal property and is more accurate,efficient and needs lower cost emulation.

关 键 词：现场可编程门阵列 错误注入模型 动态局部重配置 JTAG边界扫描 

分 类 号：N945.12[自然科学总论—系统科学]