可变码率BCH码编译码的FPGA实现  

FPGA Implementation of Coding/Decoding of Variable-rate BCH Code

作　　者：刘冀[1] 孙玲[2] 

机构地区：[1]中国电子科技集团公司第五十四研究所,河北石家庄050081 [2]石家庄供电公司科技信息部,河北石家庄050081

出　　处：《无线电工程》2010年第7期11-12,42,共3页Radio Engineering

摘　　要：为了克服LDPC的误码平台,可采用BCH码与LDPC的级联。在参考了多种编译码结构的基础上,针对二进制BCH码,介绍了适合码率可变的编译码方法,包括短时延的编码,译码中的伴随式计算、错误位置多项式的计算、错误位置的求解、逆元素的求解和相关控制存储等模块所采用的算法及FPGA实现的硬件结构。通过测试,该算法结构占用FPGA资源适中,整体硬件实现可靠,在工作时钟为150MHz时,数据吞吐速率达到100MHz以上。To overcome the defect of error floor of LDPC, BCH can be cascaded with LDPC. Based on several coding/decoding structures, the article introduces the encoding and decoding algorithm of variable-rate BCH code, including the algorithms and hardware structures for encoder with short delay time, syndrome calculation, error position polynomial calculation, error position calculation, inverse element calculation and related control and storage modules inside decoder. In practical test, this algorithm is reliable and occupies an appropriate amount of FPGA resource. When the working cloek is 150 MHz, the data transmission rate is more than 100 MHz.

关 键 词：BCH LDPC 级联码 FPGA 

分 类 号：TN92[电子电信—通信与信息系统]