基于数字后处理算法的并行交替采样ADC系统  

8-bit 4-Gsps Time-Interleaved ADC Based on Digital Post-Processing Calibration

作　　者：周浩[1] 赵雷[1] 李玉生[1] 刘树彬[1] 安琪[1] 

机构地区：[1]中国科学技术大学近代物理系,合肥230026

出　　处：《数据采集与处理》2010年第4期537-543,共7页Journal of Data Acquisition and Processing

基　　金：NSAF国家自然科学基金(10476028)资助项目;物理电子学安徽省重点实验室资助项目

摘　　要：为了在现有的模/数转换(ADC)芯片的技术条件下提高模/数转换系统的性能,在并行交替采样系统失配误差修正算法的基础上,研制了8-bit 4-Gsps并行交替采样ADC系统。该系统中4个1-Gsps ADC通道并行采样同一模拟信号;以锁相环和可调延迟线芯片为核心,组成低jitter、低skew的多相时钟产生电路,为各ADC通道提供交替采样时钟;在FPGA芯片双倍速I/O和内部集成锁相环的支持下,使用单片FPGA芯片接收ADC系统产生的高速并行数据,并完成数据同步、重排和缓存,通过USB接口读出。基于模拟数字混合滤波器组的数字后处理算法修正了各ADC通道间的增益、偏置和采样间隔三种失配误差。测试结果表明,该并行交替采样ADC系统在4-Gsps采样率下,对200 MHz与803 MHz正弦波信号分别达到6.89 b与5.81 b的ENOB以及51.81 dB和51.13 dB的SFDR,接近ADC芯片手册给出的性能。An 8-bit 4-Gsps time-interleaved ADC system based on digital post-processing calibration is designed. It consists of four 1-Gsps ADC channels with the same analog signal. The multi-phase clock generating circuit supplies the ADC channels with low jitter and low skew sampling clocks by using phase-locked loop （PLL） and delay line chips. One single FPGA, with the architecture of dual-data-rate I/O and integrated PLL, is used to receive the high- speed LVDS sampling data, to arrange data in sampling sequence and to implement the data buffer. A digital post-processing calibration algorithm based on the hybrid filter banks decreases the bad effect of the gain, the offset and time-skew mismatches, thus improving the TI- ADC performance. Experimental results show that while operating at 4-Gsps conversion rate the TI-ADC achieves 6.89 b and 5.81 b ENOB with 51.81 dB and 51.13 dB SFDR at 200 MHz and 803 MHz sinusoidal input, it is close to the datasheet performance of ADC chip in the system.

关 键 词：模/数变换 高速电路设计 数字滤波 并行交替采样 

分 类 号：TN792[电子电信—电路与系统]