一种新型全集成CMOS低噪声放大器优化设计方法  

A novel design optimization method of fully integrated CMOS low noise amplifier

作　　者：黄晓华[1] 王先锋[1] 陈抗生[1] 周金芳[1] 

机构地区：[1]浙江大学信息与电子工程学系电子信息技术与系统研究所,杭州310027

出　　处：《中国科技论文在线》2010年第1期47-51,共5页

基　　金：高等学校博士学科点专项科研基金(20060335065)

摘　　要：提出一种以几何规划作为全局搜索算法的全集成低噪声放大器优化方法。在优化过程中,将功耗、输入匹配、器件尺寸等性能参数表示为约束条件,将片上电感寄生电阻噪声和晶体管噪声表示为优化目标,从而将复杂的全集成LNA优化问题转化为一个能够进行高效求解的几何规划问题。版图后仿真结果表明,在2.4GHz工作频率下,低噪放的功耗为4.8mW,正向增益S21可达17.4dB,反射参数S11、S22均小于-20dB,三阶互调点IIP3为-4.2dBm,噪声系数NF仅为2.0dB。A geometric programming（GP）-based global optimization method of fully integrated CMOS low noise amplifier（LNA） is presented.By setting the circuit components and performance specifications of LNA as design constraints,transistor noise and parasitic resistance noise in the integrated gate inductor as optimization objective,the complicated design problem was formulated as a geometric programming problem.The results of the post-layout simulation showed that the 2.4 GHz LNA,based on CMOS technology,consumed a low DC power of 4.8 mW,noise figure of 2.0 dB,power gain S21 of 17.4 dB,S11,S22 below-20 dB,and input third-order intermodulation product of-4.2 dBm.

关 键 词：全集成 CMOS低噪声放大器 输入匹配 功耗约束 噪声优化 

分 类 号：TN722.3[电子电信—电路与系统]