面向BIT验证的总线级故障注入器设计与实现  

Design and implement of fault injection unit of VME bus fault injection system

作　　者：马毅 高小鹏[1] 

机构地区：[1]北京航空航天大学计算机体系结构研究所,100091

出　　处：《微计算机信息》2010年第23期118-120,155,共4页Control & Automation

摘　　要：为了实现对某型航空电子设备BIT(机内测试)设计的验证试验,设计了基于FPGA(现场可编程门阵列)的VME总线故障注入设备。首先根据故障注入试验的需求,给出了针对总线级故障注入系统的通用框架结构,然后结合VME总线协议的具体特点实现了VME总线故障注入器的故障注入单元。本文采用FPGA技术,给出了故障注入单元的设计实现方法,并给出了时序仿真结果。通过仿真结果,说明了故障注入单元可以完成试验要求的功能。In order to realize the verification test of certain equipment＇s BIT （build in test） design, a fault injection device of VME bus is designed based on FPGA （Field Programmable Gate Array） technology.First,base on the requirements of fault injection experiment,a universal architecture for bus level fault injection system is put forward.Then considered the specific characteristic of VME bus specification, the fault injection unit of fault injection device for VME bus is implemented.In this article, the method of design and implement fault injection unit is put forward based on FPGA technology and the timing simulation result is also showed.According to the timing simulation result, it is proved that the function of fault injection unit meets the requirement of the experiment.

关 键 词：故障注入 VME总线 FPGA 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]