基于流水线加法器的数字相关器设计  

Design of Digital Correlator Based on Pipeline Adder

作　　者：雷青锋[1] 郏文海[1] 

机构地区：[1]中国电子科技集团公司第二十研究所,陕西西安710068

出　　处：《现代电子技术》2010年第16期151-153,共3页Modern Electronics Technique

摘　　要：数字相关器在数字扩频通信系统中应用广泛,受数字信号处理器件速度限制,无法应用于高速宽带通信系统,在此提出了一种基于流水线加法器的数字相关处理算法。该算法最大限度地减少了加法器进位操作,解决了基于全加器型数字相关器存在的进位延迟过大的问题,实现了时分多址体制下的同步段数字相关,提高了同步段相关的可靠性。Digital correlator is widely applied in digital spread-spectrum communication system,but it cannot be used in high speed wide-band communication system due to the limitation of low-speed DSP device.In this paper,a full-adder based digital correlation processing algorithm is proposed,which largely decreased the carry operation in the full-adder,solved the problem of carry time-delay existing in the full-adder based digital correlator,achieved the synchronization processing in time-division-multiple-access based system and improved the reliability of the synchronization correlation.

关 键 词：扩频通信 数字相关 FPGA 流水线加法器 相关器 

分 类 号：TN911-34[电子电信—通信与信息系统]