基于低功耗的BIST测试生成结构优化设计  

Pattern generation research of BIST based on low power

作　　者：姚丽婷[1] 谈恩民[1] 

机构地区：[1]桂林电子科技大学电子工程学院,广西桂林541004

出　　处：《电子设计工程》2010年第8期71-74,共4页Electronic Design Engineering

摘　　要：针对内建自测试(Built-In Self-Test,BIST)技术的伪随机测试生成具有测试时间过长,测试功耗过高的缺点,严重影响测试效率等问题,提出一种低功耗测试生成方案,该方案是基于线性反馈移位寄存器(LFSR)设计的一种低功耗测试序列生成结构——LP-TPG(Low Power Test Pattern Generator),由于CMOS电路的测试功耗主要由电路节点的翻转引起,所以对LFSR结构进行改进,在相邻向量间插入向量,这样在保证原序列随机特性的情况下,减少被测电路输入端的跳变,以ISCAS'85基准电路作为验证对象,组合电路并发故障仿真工具fsim,可得到平均功耗和峰值功耗的降低,从而达到降低功耗的效果。验证结果表明,该设计在保证故障覆盖率的同时,有效地降低了测试功耗,缩短了测试序列的长度,具有一定的实用性。For the pseudorandom test generation of BIST has disadvantages of too much test time and high test power consumption,which influence the test efficiency severely,a low power test pattern generator based on linear feedback shift register （LFSR）,which is called LP-TPG,is presented to reduce the test power. CMOS circuit test power mainly caused by flipping the circuit nodes,the improvement of the structure of LFSR is required. LP-TPG inserts intermediate patterns between the random patterns, which reduced the transitional activities of primary inputs, as the same time the random nature of the test patterns is kept intact.ISCAS＇85 benchmark circuits and combinational circuits concurrent fault simulation tools fsim are used to confirm, which can reduce average power and peak power so as to achieve the effect of reducing power consumption. The random nature of the test patterns is kept intact. The verification results indicate this structure ensures the fault coverage ,reduces the power consumption ,and shortens the length of test sequence simultaneously. This design has some practicality.

关 键 词：线性反馈移位寄存器 LP—TPG 低功耗 平均功耗 峰值功耗 

分 类 号：TN47[电子电信—微电子学与固体电子学]