99.1 m W12位40 MSPS流水线A/D转换器  

A 99.1 m W12-Bit 40 MSPS Pipelined A/D Converter

作　　者：殷秀梅[1] 赵南[1] 杨华中[1] 

机构地区：[1]清华大学电子工程系,北京100084

出　　处：《微电子学》2010年第4期497-502,共6页Microelectronics

摘　　要：设计并实现了一种12位40 MSPS流水线A/D转换器,并在0.18μm HJTC CMOS工艺下流片。芯片工作电压为3.3 V,核心部分功耗为99.1 mW。为优化ADC功耗,采用多位/级的系统结构和套筒式运放结构,并采用逐级按比例缩小的设计方法进一步节省功耗。测试结果表明,A/D转换器的DNL小于0.46 LSB,INL小于0.86 LSB;采样率为40 MSPS时,输入19.1MHz信号,SFDR超过80 dB,SNDR超过65 dB。A 12-bit 40-MS/s pipelined A/D converter（ADC） was designed and implemented in 0.18-μm HJTC CMOS process.The core circuit drew 99.1 mW of power from 3.3 V supply.Multi-bit/stage architecture and telescope OTA were adopted to optimize power consumption of the ADC.For further power reduction,capacitor sizes and OTA current were scaled down stage by stage.Test results showed that the ADC,which is calibration-free,had a DNL less than 0.46 LSB,an INL below 0.86 LSB,an SNDR above 65 dB,and SFDR above 80 dB at Nyquist input frequency of 40 MSPS.

关 键 词：A/D转换器 流水线 CMOS 

分 类 号：TN792[电子电信—电路与系统]