Design and application of a depletion-mode NJFET in a high-voltage BiCMOS process  

作　　者：刘勇 唐昭焕 王志宽 杨永晖 杨卫东 胡永贵 

机构地区：[1]Sichuan Institute of Solid-State Circuits,CETC [2]National Laboratory of Analog ICs

出　　处：《Journal of Semiconductors》2010年第8期70-73,共4页半导体学报（英文版）

摘　　要：A novel depletion-mode NJFET compatible high-voltage BiCMOS process is proposed and experimentally demonstrated with a four-branch 12-bit DAC（digital-to-analog converter）.With this process,an NJFET with a pinch-off voltage ofabout-1.5 V and a breakdown voltage of about 16 V,an NLDDMOS（N-type lightly-dosed-drain in MOS） with a turn-on voltage of about 1.0 V and a breakdown voltage of about 35 V,and a Zener diode with a reverse voltage of about 5.6 V were obtained.Measurement results showed that the converter had a reference temperature coefficient of less than±25 ppm/℃,a differential coefficient error of less than±0.3 LSB,and a linear error of less than±0.5 LSB.The depletion-mode NJFET and its compatible process can also be widely used for high-voltage ADCs or DACs.A novel depletion-mode NJFET compatible high-voltage BiCMOS process is proposed and experimentally demonstrated with a four-branch 12-bit DAC（digital-to-analog converter）.With this process,an NJFET with a pinch-off voltage ofabout-1.5 V and a breakdown voltage of about 16 V,an NLDDMOS（N-type lightly-dosed-drain in MOS） with a turn-on voltage of about 1.0 V and a breakdown voltage of about 35 V,and a Zener diode with a reverse voltage of about 5.6 V were obtained.Measurement results showed that the converter had a reference temperature coefficient of less than±25 ppm/℃,a differential coefficient error of less than±0.3 LSB,and a linear error of less than±0.5 LSB.The depletion-mode NJFET and its compatible process can also be widely used for high-voltage ADCs or DACs.

关 键 词：depletion-mode NJFET high-voltage BiCMOS process ADC DAC temperature coefficient 

分 类 号：TN433[电子电信—微电子学与固体电子学]