4 GHz bit-stream adder based on ∑△ modulation  

作　　者：梁勇 王志功 孟桥 郭晓丹 

机构地区：[1]Institute of RF-& OE-ICs,Southeast University

出　　处：《Journal of Semiconductors》2010年第8期104-107,共4页半导体学报（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(No.60576028).

摘　　要：The conventional circuit model of a bit-stream adder based on sigma delta（∑Δ） modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit（IC） of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency.The IC is fabricated in TSMC＇s 0.18-μm CMOS process.The chip area is 475×570μm^2.A fully digital∑Δsignal generator is designed with a field programmable gate array to test the chip.Experimental results show that the chip meets the function and performance demand of the design,and the chip can work at a frequency of higher than 4 GHz.The noise performance of the adder is analyzed and compared with both theory and experimental results.The conventional circuit model of a bit-stream adder based on sigma delta（∑Δ） modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit（IC） of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency.The IC is fabricated in TSMC＇s 0.18-μm CMOS process.The chip area is 475×570μm^2.A fully digital∑Δsignal generator is designed with a field programmable gate array to test the chip.Experimental results show that the chip meets the function and performance demand of the design,and the chip can work at a frequency of higher than 4 GHz.The noise performance of the adder is analyzed and compared with both theory and experimental results.

关 键 词：bit-stream ADDER sigma delta digital signal generator 

分 类 号：TN405[电子电信—微电子学与固体电子学]