A low jitter,low spur multiphase phase-locked loop for an IR-UWB receiver  

作　　者：邵轲 陈虎 潘姚华 洪志良 

机构地区：[1]State Key Laboratory of ASIC and System,Fudan University

出　　处：《Journal of Semiconductors》2010年第8期121-125,共5页半导体学报（英文版）

基　　金：Project supported by the National High Technology Research and Development Program of China(No.2009AA01Z261);the State Key Laboratory of Wireless Telecommunication,Southeast University,China.

摘　　要：A low jitter,low spur multiphase phase-locked loop（PLL） for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator（VCO） is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the loop filter bandwidth,the reference spur is suppressed. A phase noise of-118.42 dBc/Hz at a frequency offset of 1 MHz,RMS jitter of 1.53 ps and reference spur of-66.81 dBc are achieved at a carrier frequency of 264 MHz in measurement.The chip was manufactured in 0.13μm CMOS technology and consumes 4.23 mW from a 1.2 V supply while occupying 0.14 mm^2 area.A low jitter,low spur multiphase phase-locked loop（PLL） for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator（VCO） is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the loop filter bandwidth,the reference spur is suppressed. A phase noise of-118.42 dBc/Hz at a frequency offset of 1 MHz,RMS jitter of 1.53 ps and reference spur of-66.81 dBc are achieved at a carrier frequency of 264 MHz in measurement.The chip was manufactured in 0.13μm CMOS technology and consumes 4.23 mW from a 1.2 V supply while occupying 0.14 mm^2 area.

关 键 词：PLL MULTIPHASE ring oscillator RMS jitter reference spur IR-UWB 

分 类 号：TN851[电子电信—信息与通信工程]