一种FFT并行处理机的设计与实现  

Design and implementation of the FFT parallel processor based on ASIP

作　　者：张犁[1] 李双飞[1] 石光明[1] 李甫[1] 

机构地区：[1]西安电子科技大学电子工程学院,陕西西安710071

出　　处：《西安电子科技大学学报》2010年第4期630-635,共6页Journal of Xidian University

基　　金：国家"863"高科技基金资助项目(2007AA01Z307)

摘　　要：专用指令集处理器具有数字信号处理器的可编程性和专用处理电路的高速性,以专用指令集处理器为核心构成的阵列式并行处理系统在高速实时处理方面有着非常重要的应用.为此,提出了一种基于专用指令集处理器的快速傅里叶变换并行处理机实现方法.设计了基于精简指令集处理器体系结构的可编程处理单元,以其为核心构成并行处理系统,采用通信矩阵解决了并行系统内各个处理单元间的数据交换问题,实现了1 024点快速傅里叶变换的并行处理.实验结果表明,在快速傅里叶变换处理方面,其处理速度比典型数字信号处理器提高30%,且具有系统并行规模大、功能灵活可变、设计复杂程度适当、设计重复利用性好的优点,非常适合在现场可编程逻辑门阵列中以SoC的形式实现.The ASIP combines programmability of DSP and high speed of ASIC,and the parallel array processing system based on it plays an important role in the high-speed and real-time processing applications.An implementation of 1024 points FFT parallel processor based on the ASIP is presented in this paper.An ASIP with the reduced instruction set computer（RISC） architecture is designed as the processing element（PE）,which constructs the kernel of the parallel processing system.In addition,the communication matrix is adopted to achieve the data exchange between PEs.Experimental results show that,compared with the typical DSP,the new proposed architecture improves the processing speed by 30%.Furthermore,this system has the advantages of larger parallel scale,greater function adaptability,relatively lower designing complexity and greater design reuse ability.So it can be achieved in a single FPGA in the form of SoC.

关 键 词：专用指令集处理器 快速傅里叶变换 精简指令集处理器 并行处理 数据通信 

分 类 号：TN302.1[电子电信—物理电子学]