AES和Camellia算法的可重构硬件实现  

Reconfigurable Hardware Implementation of AES and Camellia Algorithm

作　　者：杨宏志[1] 韩文报[1] 李光松[1] 

机构地区：[1]解放军信息工程大学信息工程学院,郑州450002

出　　处：《计算机工程》2010年第16期18-20,共3页Computer Engineering

基　　金：国家自然科学基金资助重大项目(90104035);国家"863"计划基金资助项目(2006AA01Z425)

摘　　要：AES算法和Camellia算法是应用最广泛的分组密码算法,其可重构性和高速实现具有重要的理论意义和实用价值。在对算法原理进行分析的基础上,研究AES和Camellia算法的可重构性,基于S盒变换,利用并行处理和重构技术,给出它们的可重构体系结构,并在此基础上高速实现了AES、Camellia算法。实验结果表明,采用该设计方案,算法实现速度快,电路资源开销小。AES and Camellia are the two most widely used block cipher algorithms.The reconstruction and high-speed implementation characteristics of them are very important in both theories and practices.In this paper,on the foundation of analyzing the algorithms,the reconfiguration of AES and Camellia is studied.Based on the S-box transformation,reconfigurable architecture of the two algorithms is given by parallel processing and reconfigurable technology.Moreover,high-speed realizations of AES and Camellia algorithms are proposed using the reconfigurable architecture.Testing results show the scheme has a higher speed and it can reduce the area cost greatly.

关 键 词：分组密码 可重构 S盒 

分 类 号：TP311.52[自动化与计算机技术—计算机软件与理论]