基于FPGA的HDB3编解码器的设计与实现  

Design of HDB3 CODEC Based on FPGA and Its Implementation

作　　者：韩德红[1] 孙筱萌[1] 张显才[1] 

机构地区：[1]空军雷达学院三系,武汉430019

出　　处：《空军雷达学院学报》2010年第4期274-276,280,共4页Journal of Air Force Radar Academy

摘　　要：为了满足基带传输系统中传输码型无直流分量、低频分量少、便于提取定时时钟和具有一定的检错能力等要求,选择HDB3码并结合FPGA集成度高、速度快的特点,用ALTERA公司的Cyclone系列FPGA芯片EP2C8T144C6实现了HDB3编解码电路的设计.该设计提高了整个通信系统的集成度,克服了分立硬件电路带来的抗干扰差和不易调整等缺陷.实验结果表明:系统的传输误码率低于10 6.该设计可应用到实际的通信系统传输中.In order to meet the demands of transmission codes’no DC component,less low frequency components and easier timing clock extraction as well as a certain error detection capability in the baseband transmission system,the HDB3 code was selected,and the design of HDB3 co-decoder circuits implemented by using the EP2C8T144C6 FPGA chip in Cyclone series of ALTERA Inc.and in terms of the high integration level and fast speed of FPGA chips,improving the integration level of entire communication system and precluding the poor anti-jamming,hard-adjusting and other drawbacks resulted from the discrete hardware circuits.Experimental results show that transmission bit error rate of system is less then 10 6,and the design can be applied to the real communication transmission.

关 键 词：HDB3编解码 现场可编程门阵列 VHDL语言 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]