40Gbps甚短距离并行光传输系统接收电路的设计与实现  

Receiver design and realization of 40Gbps very short reach optical transmission systems

作　　者：许多[1] 胡庆生[1] 苗澎[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《高技术通讯》2010年第1期82-88,共7页Chinese High Technology Letters

基　　金：863计划(2006AA01Z239)资助项目

摘　　要：给出了符合OIF-VSR5规范的40Gbps甚短距离光传输系统接收电路的设计与实现。该接收电路实现简单,由一片转换芯片及光接收模块构成。其特点是充分利用现场可编程门阵列(FPGA)内嵌的高速收发器成功实现了16×2.488Gbps和12×3.318Gbps信号的发送和接收,并且在一片FPGA上实现了诸如时钟数据恢复、串/并转换、帧同步、通道对齐、12-16路映射等全部功能。基于二分查找法的帧同步电路则大大提高了转换芯片的工作速度。Signaltap Ⅱ逻辑分析仪的测试结果表明接收电路工作正常,性能良好。在此基础上,给出了VSR5实验系统的点到点测试方法,通过12通道垂直腔面发射激光器并行接收模块和7m 12芯多模带状光纤,将发送电路与接收电路相连,实现了OC768/STM-256 40Gbps的点到点测试,测试结果表明系统误码率小于10^(-12)。The paper presents the receiver design and realization of a 40Gbps very short reach （VSR） optical transmission system compatible for the OIF-VSR5 specification. The receiver consists of a converter IC and an optical receiver module, characterized by making full use of high speed transceivers in the field-programmable gate array （FPGA） to successfully realize 16×2.488 Gbps and 12 ×3.318Gbps signal transmission and reception. All of the functions of the converter IC such as clock data recovery, serial/parallel conversion, frame synchronization, channel deskew, 12/16 conversion and channel rearrangement are implemented in one FPGA chip. The frame synchronization logic based on the binary search al- gorithm can speed up the converter IC greatly. Testing results obtained from Signaltap II indicate that the circuit works well and correctly. Furthermore, this paper presents a point-to-point test of the VSR5 experiment system. By connecting transmitter and receiver through 7-meter 12-fiber multi-model ribbon, a SDH STM-256/OC768 40Gbps point-to-point test was realized, and a low bit error rate of 10^-12 was obtained.

关 键 词：VSR5 转换芯片 帧同步 通道对齐 12-16路映射 

分 类 号：TN929.1[电子电信—通信与信息系统]