基于0.18μm CMOS工艺的2 Gsps 6比特全并行模数转换器设计  

A 2-Gsps 6-bit flash analog-to-digital converter in 0.18-μm CMOS process

作　　者：刘海涛[1] 孟桥[1] 王志功[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《高技术通讯》2010年第2期180-184,共5页Chinese High Technology Letters

基　　金：863计划(2007AA01Z2A7)资助项目

摘　　要：基于0.18μm CMOS工艺,研究并设计了一个精度为6比特、采样率为2 Gsps的全并行超高速模数转换器(ADC),发现并解决了门限限速效应(TLSE),进而提高了ADC的电压比较器的工作速度,并利用平均终端法减小了电路非线性失真。采用分段编码方式,使电路规模和速度都得到了优化。通过SMIC实现流片,有效面积为0.48mm^2。实测结果表明,该ADC芯片的最小分辨率为10mV,最高采样率可达2.2Gsps。最高采样率下有效位达到5.6比特,总功耗310mW。This paper presents the design and test of a 2-Gsps 6-bit flash type analog-to-digital converter （ADC） in the 0.18μm CMOS technology. The speed of the ADC＇ s comparator is promoted by solving the problem of threshold-limitspeed effect （TLSE）. The non-linear errors are reduced by means of averaging the terminations. The area and speed of the encoder part are optimized by the segmented encoding. The IC is realized in the SMIC 0.18μm CMOS technology, which occupies an active area of 0.48mm^2. The measurements show the ADC＇ LSB of 10 mV and the reachable sampling rate of 2.2 Gsps. At 2.2 Gsps the effective number of bits （ENOB） can reach 5.6 bits and the power consumption is 310mW.

关 键 词：模数转换器(ADC) 全并行 CMOS 超高速 

分 类 号：TN792[电子电信—电路与系统]