基于FPGA的自适应锁相环设计  

Design of adaptive phase locked loop based on FPGA

作　　者：何苏勤[1] 詹明静[2] 

机构地区：[1]北京化工大学DSP实验室,北京100029 [2]北京化工大学计算机应用技术系,北京100029

出　　处：《电子设计工程》2010年第9期147-150,154,共5页Electronic Design Engineering

基　　金：国家自然科学基金资助项目(50975019)

摘　　要：利用锁相环进行载波跟踪是获取本地载波的一种重要方法,针对锁相环的噪声性能和跟踪速度不能同时达到最优的限制,在锁相环PLL中引入自适应模块,根据环路所处的环境自适应对PLL环路参数做出调整。设计中利用仿真软件MATLAB对自适应锁相环进行仿真,并在FPGA硬件板上利用VHDL编程实现。在载波信号为10 MHz、采样率为80 MHz的条件下,设计的自适应锁相环在噪声水平较小时跟踪速度提高了0.5μs左右,在噪声水平较高时相位抖动降低了0.01 rad左右。Acquiring the local carrier with the phase locked loop is an important method. In allusion to the limit that the noise performance and the trace speed can＇t be optimized at the same time. in this paper the design added adaptive modules to the conventional PLL, which adjusted the parameters according to the current condition. This design simulated the adaptive PLL with MATLAB, and fulfilled the loop in VHDL on the FPGA. When the frequency of the carrier is 10MHz and the sampling frequency is 80MHz, the adaptive PLL designed in this article improves the trace time by about 5 μs when the noise level is low, and decrease the phase dithering by about 0.01 rads.

关 键 词：相干解调 PLL FPGA EP3C10F256C8 

分 类 号：TN911[电子电信—通信与信息系统]