基于FPGA的十进制浮点乘法器的设计与研究  

A decimal floating-point multiplier based on FPGA and its research

作　　者：唐佐侠[1] 杨军[1] 董寅[1] 

机构地区：[1]云南大学信息学院,云南昆明650091

出　　处：《云南大学学报（自然科学版）》2010年第5期526-531,共6页Journal of Yunnan University(Natural Sciences Edition)

基　　金：云南省教育厅科学研究基金重点资助项目(09C0011)

摘　　要：以IEEE-754r这个新的标准为基础给出了一个基于FPGA的十进制浮点乘法器模型.由于新标准的修订和十进制浮点乘法运算的应用广泛性,本模型设计在医疗和金融行业,以及图像处理技术方面具有一定的实际意义.模型采用新型BCD编码及Signed-Digitradix-4算法进行十进制浮点数分解运算.与二进制浮点运算相比,具有运算范围更宽、计算精度更高、应用范围更广等特点.A double-precision decimal floating-point multiplier unit based on FPGA technology is given in this paper.It is a new revision according the IEEE-754r standard.It uses Signed-Digit radix-4 algorithm and new BCD coding techniques for the decomposition of decimal floating-point computing.Compared with the commen single-precision binary floating-point unit,it is wider computing,higher accuracy and wider application.The design takes advantage of the revision of new standard,and decimal floating-point multiplier unit has broad applicability.All these make this model have some practical value in medical,financial and image processing.

关 键 词：十进制浮点乘法器 Signed-Digitradix-4 余三码 BCD编码 DPD编码 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]