An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB  

作　　者：樊华 魏琦 Kobenge Sekedi Bomeh 殷秀梅 杨华中 

机构地区：[1]Division of Circuits and Systems,Department of Electronic Engineering,Tsinghua University

出　　处：《Journal of Semiconductors》2010年第9期118-122,共5页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.60976032)

摘　　要：This paper presents a differential successive approximation register analog-to-digital converter（SAR ADC） with a novel time-domain comparator design for wireless sensor networks.The prototype chip has been implemented in the UMC 0.18-μm 1P6M CMOS process.The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz.With the Nyquist input frequency,68.49-dB SFDR,7.97-ENOB is achieved.A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout.The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.This paper presents a differential successive approximation register analog-to-digital converter（SAR ADC） with a novel time-domain comparator design for wireless sensor networks.The prototype chip has been implemented in the UMC 0.18-μm 1P6M CMOS process.The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz.With the Nyquist input frequency,68.49-dB SFDR,7.97-ENOB is achieved.A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout.The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.

关 键 词：successive approximation register time-domain comparator analog-to-digital converter 

分 类 号：TN432[电子电信—微电子学与固体电子学]