A 2-GS/s 6-bit self-calibrated flash ADC  

作　　者：张有涛 李晓鹏 张敏 刘奡 陈辰 

机构地区：[1]National Key Laboratory of Monolithic Integrated Circuits and Modules,Nanjing Electronic Devices Institute [2]Nanjing Electronic Devices Institute

出　　处：《Journal of Semiconductors》2010年第9期129-133,共5页半导体学报（英文版）

摘　　要：A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μm CMOS.The calibration method based on DAC trimming improves the linearity and dynamic performance further.The peak DNL and INL are measured as 0.34 and 0.22 LSB,respectively.The SNDR and SFDR have achieved 36.5 and 45.9 dB,respectively,with 1.22 MHz input signal and 2 GS/s.The proposed ADC,including on-chip track-and-hold amplifiers and clock buffers,consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s.A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μm CMOS.The calibration method based on DAC trimming improves the linearity and dynamic performance further.The peak DNL and INL are measured as 0.34 and 0.22 LSB,respectively.The SNDR and SFDR have achieved 36.5 and 45.9 dB,respectively,with 1.22 MHz input signal and 2 GS/s.The proposed ADC,including on-chip track-and-hold amplifiers and clock buffers,consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s.

关 键 词：analog-to-digital conversion offset averaging FLASH INTERPOLATION CALIBRATION 

分 类 号：TN792[电子电信—电路与系统] TP274.2[自动化与计算机技术—检测技术与自动化装置]