A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-μm CMOS  

作　　者：张章 袁宇丹 郭亚炜 程旭 曾晓洋 

机构地区：[1]State Key Laboratory of ASIC & System,Fudan University

出　　处：《Journal of Semiconductors》2010年第9期134-140,共7页半导体学报（英文版）

基　　金：supported by the National High Technology Research and Development Program of China(No.2009AA011600);the Project for Young Scientists Fund of Fudan University,China(No.09FQ33);the State Key Laboratory ASIC & System(Fudan University), China(No.09MS008)

摘　　要：A 10-bit 30-MS/s pipelined analog-to-digital converter（ADC） is presented.For the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages. The ADC is realized in the 0.13-μm 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range,poor analog characteristic devices,the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference.Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio,67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7- MHz input signal.The FoM is 0.33 pJ/step.The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB,respectively.The ADC core area is 0.94 mm^2.A 10-bit 30-MS/s pipelined analog-to-digital converter（ADC） is presented.For the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages. The ADC is realized in the 0.13-μm 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range,poor analog characteristic devices,the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference.Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio,67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7- MHz input signal.The FoM is 0.33 pJ/step.The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB,respectively.The ADC core area is 0.94 mm^2.

关 键 词：analog-to-digital converter PIPELINED sampling capacitor two-stage op amp compensation linearity of analog switch sub-1-V bandgap voltage reference 

分 类 号：TN432[电子电信—微电子学与固体电子学]