UHF RFID阅读器中低噪声Σ小数频率综合器的设计  

A Low Phase Noise ΔΣ Fractional-N Frequency Synthesizer for UHF RFID Reader

作　　者：何伟[1] 徐萍[1] 张润曦[1] 石春琦[1] 张勇[1] 陈子晏[1] 赖宗声[1] 

机构地区：[1]华东师范大学微电子电路与系统研究所,上海200062

出　　处：《固体电子学研究与进展》2010年第3期408-412,共5页Research & Progress of SSE

基　　金：上海AM基金资助项目(07SA04);上海重点学科建设项目(B411)

摘　　要：采用0.18μmRF CMOS工艺结合EPC C1G2协议和ETSI规范要求,实现了一种应用于CMOS超高频射频识别阅读器中的低噪声ΔΣ小数频率综合器。基于三位三阶误差反馈型ΔΣ解调器,采用系数重配技术,有效提高频率综合器中频段噪声性能;关键电路VCO的设计过程中采用低压差调压器技术为VCO提供稳定偏压,提高了VCO相位噪声性能。多电源供电模式下全芯片偏置电流为9.6mA,测得在中心频率频偏200kHz、1MHz处,相处噪声分别为-108dBc/Hz和-129.8dBc/Hz。A low phase noise fractional-N frequency synthesizer for CMOS UHF RFID reader is introduced in this paper. The phase noise requirements are summarized for the EPC global CIG2 and ETSI multi-protocol operation. A low drop-output regulator is presented to improve the phase noise performance of the VCO. Based on the error-feedback delta-sigma modulator, a coefficient reconfiguring technology has been introduced to improve the phase noise performance at intermediate frequency band. The proposed circuit is implemented with 0. 18 μm RF CMOS process. The fractional-N frequency synthesizer achieves a phase noise of -108 dBc/Hz and --129.8 dBc/Hz at 200 kHz and 1 MHz offset from the carrier respectively. The whole chip draws 9.6 mA from the multiple power supply configuration.

关 键 词：超高频射频识别 相位噪声 频率综合器 调制器 

分 类 号：TN76[电子电信—电路与系统] TN74