基于SV语言的DBA芯片的验证  

Logic Verification for 10G EPON DBA Based on SV

作　　者：董宝贵[1] 张长明[1] 欧家成[1] 

机构地区：[1]电子科技大学光电信息学院,四川成都610054

出　　处：《通信技术》2010年第9期173-176,共4页Communications Technology

摘　　要：随着芯片规模和设计复杂度的增加,传统的模拟验证方法学已经成为整个验证的瓶颈。为了解决这一瓶颈问题,验证方法学从模拟验证逐步演变成形式验证,先后经过了模拟晶体管模型仿真、门级仿真以及采用点线功能模型(BFM)的事务级仿真三个阶段。SV验证方法学是在模拟验证的基础上增加了形式验证的方法;它采用以覆盖率为导向的技术、受约束的随机技术和基于断言的技术来构建全面的验证环境。以覆盖率为导向可使验证迅速达到验证的出口条件,采用随机测试用例为主代替传统的直接测试为主可使验证迅速收敛,而通过在设计中插入断言可精确验证设计的内部时序问题。实践结果表明,采用这种验证方法极大的提高了验证的效率,缩短了验证周期。With increase of the chip size and design complexity,traditional analog verification methodology becomes the bottleneck of the whole verification.To solve this problem,the verification methodology evolves from analog verification to formal verification,involving three phases of analog simulation of transistor model,gate-level simulation and transaction-level simulation with BFM.SV verification is a method in addition of formal verification method to analog verification method,and with the coverage-oriented technology,constrained-random technology and SVA technology,constructs a comprehensive verification environment.Coverage-driven verification could quickly achieve verification export conditions.Random test case-based test in place of traditional direct test allows the rapid verification convergence,and the insertion of assertions in the design could accurately verify the design of internal timing.Practical results show that,this method could greatly improve the efficiency of verification and shorten the verification cycle.

关 键 词：SV语言 VMM架构 DBA[1] 动态带宽分配[2] 验证方法学 

分 类 号：TP393.04[自动化与计算机技术—计算机应用技术]