130nm PDSOI DTMOS体延迟研究  

Study on Body Delay of 130 nm PDSOI DTMOS

作　　者：毕津顺[1] 韩郑生[1] 海潮和[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2010年第9期868-870,共3页Semiconductor Technology

基　　金：国家重点基础研究资助项目(2006CB302701)

摘　　要：研究了基于IBM 8RF 130 nm工艺部分耗尽绝缘体上Si(PDSOI)动态阈值晶体管(DTMOS)体电阻、体电容以及体电阻和体电容乘积(体延迟)随Si膜厚度和器件宽度的变化。结果表明,Si膜厚度减小会导致体阻增大、体电容减小,但是体电阻和体电容的乘积却明显增大。Si膜厚度从200 nm减小到80 nm,体延迟增加将近两个数量级。器件宽度增加使得体电阻和体电容都明显增大,DTMOS电路延迟也因此指数递增。推导出了PDSOI DTMOS的延迟模型,为SOI DTMOS器件设计提供了参考。PDSOI DTMOS based on IBM 8RF twin well 130 nm technology was simulated numerically. Body resistance, body capacitance and their product （body delay） variation with top Si film thickness and device width were studied. The results show that when the thickness of the top Si film is reduced, the body resistance is increased and body capacitance is reduced, but their product is obviously increased. Body delay is increased almost two orders of magnitude with top Si film thickness from 200 nm to 80 nm. Body delay of DTMOS is increased exponentially with device width. Delay model of PDSOI DTMOS was derived. It＇s helpful for SOI DTMOS device design.

关 键 词：部分耗尽绝缘体上硅 动态阈值晶体管 体电阻 体电容 延迟 

分 类 号：TN386.1[电子电信—物理电子学]