基于FPGA的低杂散小容量DDFS设计  

Design of DDFS with Low Spurious and Small-capacity Based on FPGA

作　　者：应文威[1] 蒋宇中[1] 张伽伟[1] 

机构地区：[1]海军工程大学,湖北武汉430033

出　　处：《现代电子技术》2010年第18期13-16,共4页Modern Electronics Technique

摘　　要：研究传统的DDFS频谱杂散分量,分析了杂散分量的来源和传统相位抖动除噪技术的缺点,提出了对相位舍入分解进行Taylor展开的DDFS改进结构。同时该结构采用循环相位累加器等结构,降低了杂散分量,提高了频率精度,压缩了ROM的容量。FPGA上的实现表明该结构能有效降低杂散,能使SDFR比采用相位抖动除噪的方法扩大30 dB,同时ROM的容量比传统结构压缩了4倍以上。The traditional DDFS spurious spectral component is researched, the source of spurious noise and the disadvantage of traditional phase jitter noise canceling technology are analyzed, then a new architecture of DDFS based on the Taylor series approximation of the phase rounding decomposition is proposed. This architecture effectively i＇educed the spurious noise of the output signal, increased accuracy of the frequency, and compressed the volume of ROM. The realization based on FPGA shows that this architecture can reduce spurious noise effectively, the SDFR broadened 30db more than that of the tech- nology of phase jitter and the volume of ROM compressed four times more than that of the classic architecture.

关 键 词：DDFS FPGA TAYLOR 杂散抑制 循环相位累加器 

分 类 号：TN911-34[电子电信—通信与信息系统]