高速全数字解调器的一种在线调试方法  

An online debugging method for high speed all digital demodulator

作　　者：姜波[1] 孙晓磊[1] 

机构地区：[1]海军潜艇学院,山东青岛266071

出　　处：《电子技术应用》2010年第10期57-59,共3页Application of Electronic Technique

基　　金：国家部委预研基金资助项目(113030401)

摘　　要：提出一种高速全数字解调器的在线调试方法,灵活运用FIFO捕获并缓存包含错误信息的相关数据,解决了高速、海量数据流中难以捕获偶发性错误信息的难题,为程序缺陷分析提供条件,可直接用于高速全数字解调器的后期调试,其基本思想适应于其他高速逻辑的FPGA调试。This paper proposes an online debugging method for high speed all digital demodulator. FIFOs are artfully used to capture and to buffer the datas including error information. The method resolves the difficult problem of capturing the sporadic errors in numerous high speed data stream, offering precondition for program debugging. The proposed method can direct works for the late debugging of high speed all digital demodulators, and its basic ideas adapt to the dubugging of other high speed logic in FPGA.

关 键 词：全数字解调器 FIFO 调试 FPGA 

分 类 号：TN911.72[电子电信—通信与信息系统]