10位100MSPS 70mW双通道交织流水线A/D转换器  

A 10-Bit 100-MHz 70-mW 2-Channel Time-Interleaved Pipelined ADC

作　　者：许莱[1] 殷秀梅[1] 杨华中[1] 

机构地区：[1]清华大学电子工程系,北京100084

出　　处：《微电子学》2010年第5期621-626,共6页Microelectronics

摘　　要：设计了应用于3G无线通信中频接收机的10位100 MSPS双通道交织流水线A/D转换器,采用0.18μm CMOS工艺流片。电路工作电压为3.3 V,核心部分功耗不超过70mW。为了减小A/D转换器的功耗,采用两路并行交织结构,并在两个通道间进行运放共享。运放采用套筒式结构,以进一步节省功耗。对于交织结构,如何保证线性度是设计的关键。线性度主要受直流失调失配、增益失配及采样时间失配的限制。分别采用共享运放、提高每个通道的精度,以及全局被动采样(Global Passive Sampling),减小这些失配的影响。除通道间失配外,还分析了传统双采样电路中的输出开关电荷注入以及断开开关电容串扰对线性度的影响。为了保证A/D转换器的线性度,通过修改时序,消除了以上开关的非理想因素。后仿真结果表明,在100 MSPS采样率下,输入信号带宽为47.6 MHz;最差工艺角(ss,120℃)下,杂散无失真动态范围(SFDR)大于70 dB,信杂比(SNDR)大于60 dB。A 10-bit 100 MHz 2-channel time-interleaved pipelined A/D converter for IF receiver in 3G wireless communication was designed and implemented in 0.18-μm HJTC CMOS process.The ADC consumes less than 70 mW of power from 3.3 V supply.Op-amp sharing and telescopic structure were used to reduce power consumption of the ADC.Linearity of interleaved ADC is limited by offset mismatch,gain mismatch and time skew mismatch of channels.In this circuit,op-amp sharing,increasing accuracy of every channel and global passive sampling were adopted to reduce effects of these mismatches.Also,linearity deterioration caused by charge injection of the output switch and crosstalk of the off-switch capacitor was investigated,and non-idealities of the switches were removed by modifying clock signal arrangement,thus significantly improving linearity of the time-interleaved ADC.Results from post-layout simulation showed that the 2-channel time-interleaved ADC had an input signal bandwidth of 47.6 MHz at a sampling rate of 100 MSPS,and at the worst process corner（ss,120 ℃）,it had an SFDR over 70 dB and an SNDR above 60 dB.

关 键 词：交织 A/D转换器 运放共享 电荷注入 电容串扰 

分 类 号：TN792[电子电信—电路与系统]