基于九管存储单元的嵌入式SRAM设计  

Design of Embedded SRAM Based on 9T Cells

作　　者：区夏[1] 彭力[1,2] 王澧[2] 

机构地区：[1]江南大学信息工程学院,江苏无锡214122 [2]中国电子科技集团公司第58研究所,江苏无锡214061

出　　处：《微电子学》2010年第5期727-731,共5页Microelectronics

基　　金：江苏省自然科学基金资助项目(BK2007026)

摘　　要：为了解决深亚微米及纳米尺寸下SRAM设计在可靠性及其他性能方面所面临的挑战,在分析不同存储单元的基础上,提出了一种优化的具有高稳定性的九管存储单元,并采用9管存储阵列,设计了一款高可靠性的512×32位SRAM。基于TSMC 0.18μm CMOS工艺,对电路进行仿真。实验结果表明:该SRAM在250MHz工作频率下,存储阵列中数据的读写稳定性高,阵列功耗为7.76mW,数据读出时间为0.86ns,电路面积仅比采用传统6管单元增加13.5%。To improve the reliability and performance of SRAM in submicron and nanoscale processes,an optimized 9T-cell with high stability was proposed based on analysis of different SRAM cells.Using the 9T memory array,a 512×32 bit SRAM with high reliability was designed.Simulation based on TSMC＇s 0.18 μm CMOS process showed that,operating at 250 MHz,the SRAM had a read time of 0.86 ns,and the memory array consumed a power of 4.31 mW.The proposed design could provide the highest data stability with a chip area only 13.5% larger than conventional SRAM using 6T memory array.

关 键 词：SRAM 静态噪声容限 9管存储阵列 

分 类 号：TN432[电子电信—微电子学与固体电子学]