低压、宽带、高稳定性运放芯片设计  

Low-Voltage High-Speed integrated OP-AMP Chip with High Stability Based on 0.18umCMOS Process

作　　者：赵明剑[1] 王卫东[1] 赵秋明[1] 

机构地区：[1]桂林桂林电子科技大学信息与通信学院,广西541004

出　　处：《微计算机信息》2010年第29期190-191,196,共3页Control & Automation

基　　金：基金申请人:王卫东;项目名称:开关电流-模拟取样数据集成电路技术的研究;基金颁发部门:广西壮族自治区教育厅(桂科基0731021)

摘　　要：本论文基于0.18um CMOS标准工艺,设计了一个工作电压为1.8V的高速、宽带、高稳定性的集成运算放大器芯片。设计中采用弥勒补偿电容结合调零电阻补偿技术并且集成三支路基准电流源与高输出阻抗的低压共源共栅偏置电流分配电路,有效地提高了系统的稳定性和速度,并具有优良电源抑制比和较大的输出摆幅。最后利用Cadence Spectre仿真器对芯片版图进行后端仿真验证,芯片功耗3mW,电源抑制比-96dB,当负载电阻为1M、负载电容为1pF时,芯片开环直流电压增益为64dB,单位增益带宽为930MHz,相位余度为108o,建立时间为5.5ns,摆率为250V/us,输出摆幅为0.116～1.56V。仿真结果表明,本设计芯片可应用于中频段的放大、模拟运算、有源滤波、AGC等系统中,尤其能满足如处理微弱信号等的高性能系统的需求。This paper proposed a high -speed,broadband integrated op -amp chip with high stability based on the 0.18um CMOSstandard technology in 1.8V supply. Stability,speed,excellent power supply rejection ratio （PSRR） and larger output swing were im-proved effectively by using Miller compensation capacitor in combination with zeroing resistors compensation technique,which threebranch current reference with low-voltage Cascode bias current distribution circuit is integrated. The post simulation of the chip indi-cates that the chip had PSRR of -96dB with only 3mW of power,that had an open-loop DC voltage gain of 64 dB,GB of 930MHz,phase redundancy of 108o,settling time of 5.5ns,slew rate of 250V/us and the output swing of 0.116～1.56V under load resistanceis 1M and the load capacitance is 1pF. It showed that this design can be applied in amplification at middle-frequency,analog com-puting,active filtering,AGC system,and particularly met the demands of dealing with weak signals of high-performance systems.

关 键 词：高稳定性 调零电阻 弥勒补偿 集成运算放大器 

分 类 号：TN492[电子电信—微电子学与固体电子学]