高速单载波超宽带系统中Rake接收机的设计  

Design of a Rake receiver for high speed single carrier ultra-wideband systems

作　　者：耿春华[1] 裴玉奎[1] 葛宁[1] 闻武杰[1] 

机构地区：[1]清华大学电子工程系,北京100084

出　　处：《高技术通讯》2010年第9期950-954,共5页Chinese High Technology Letters

基　　金：863计划(2007AA01Z2B3);国家自然科学基金(60928001)资助项目

摘　　要：针对长多径时延扩展环境下的直接序列扩频单载波超宽带系统,提出了一种全数字Rake接收机的分级实现的设计方法。该设计方法利用两级移位寄存器和两级多路选择器实现Rake接收机的多径分离部分。与传统的Rake接收机设计相比,此文提出的等效方案可以有效地降低硬件资源消耗,避免布线拥塞,适合于采用现场可编程门阵列(FPGA)和专用集成电路(ASIC)实现。而且,该设计可以在传输过程中灵活选择多径分量以满足跟踪定时偏差的要求。此外,还给出了基于SMIC 0.18μm CMOS工艺下的超宽带接收机版图。A two-stage digital Rake receiver design is presented for direct-sequence spreading based single carrier ultra-wideband （SC-UWB） systems in scenarios of long channel delay spread. In this design, two stages of shift registers and two stages of multiplexers are employed for multipath separation. Compared with the conventional design, the proposed scheme obtains the same performance but reduces the hardware resource consumption significantly and avoids routing congestion in high speed UWB systems, so it is suitable for implementation of the Rake receiver using FPGA and ASIC. Moreover, the presented Rake receiver can change the selection of muhipath components flexibly to track the timing jitter in transmission. The layout of the UWB receiver based on the SMIC 0.18μm CMOS technology is also given.

关 键 词：超宽带 RAKE接收机 布线拥塞 现场可编程门阵列(FPGA) 专用集成电路 (ASIC) 

分 类 号：TN851[电子电信—信息与通信工程]