基于边界扫描技术的板级测试性优化设计  

Optimizing Design of Board Level for Testability Based on Boundary Scan Technique

作　　者：陈星[1] 吕晓明[1] 刘晓芹[1] 

机构地区：[1]军械工程学院军械技术研究所,河北石家庄050000

出　　处：《军械工程学院学报》2010年第4期63-65,75,共4页Journal of Ordnance Engineering College

摘　　要：介绍了边界扫描技术的基本原理,论述了板级电路测试性设计的思想,提出一种基于二进制粒子群算法的板级电路测试性设计最小化优化方法。实验结果表明,该算法在优化效果、运算时间上均获得了较好的结果。This paper expatiates the principle of BST and discusses the theory of board level-DFT. As the experiment shows, this algorithm can get better results on optimizing effectiveness and run-time. It proves that this algorithm can be applied in optimization of board level design for testability, and it is helpful for improving the circuit testability.

关 键 词：边界扫描 测试性设计 测试性改善 设计复杂性 二进制粒子群优化 

分 类 号：TP206[自动化与计算机技术—检测技术与自动化装置]