A 10-bit 200-kS/s SAR ADC IP core for a touch screen SoC  

作　　者：佟星元 杨银堂 朱樟明 盛文芳 

机构地区：[1]Institute of Microelectronics,Xidian University [2]Corp D.S.,Semiconductor Manufacturing International Corporation

出　　处：《Journal of Semiconductors》2010年第10期121-125,共5页半导体学报（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Nos.60725415,60971066,60676009,60776034,60803038);the National High-Tech Research and Development Program of China(Nos.2009AA01Z258,2009AA01Z260);the National Science & Technology Important Project of China(No.2009ZX01034-002-001-005)

摘　　要：Based on a 5 MSBs （most-significant-bits）-plus-5 LSBs （least-significant-bits） C-R hybrid D/A conver sion and low-offset pseudo-differential comparison approach, with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method, an 8-channel 10-bit 200-kS/s SAR ADC （successiveapproximation-register analog-to-digital converter） IP core for a touch screen SoC （system-on-chip） is implemented in a 0.18 μm 1P5M CMOS logic process. Design considerations for the touch screen SAR ADC are included. With a 1.8 V power supply, the DNL （differential non-linearity） and INL （integral non-linearity） of this converter are measured to be about 0.32 LSB and 0.81 LSB respectively. With an input frequency of 91 kHz at 200-kS/s sampling rate, the spurious-free dynamic range and effective-number-of-bits are measured to be 63.2 dB and 9.15 bits respectively, and the power is about 136 μW. This converter occupies an area of about 0.08 mm^2. The design results show that it is very suitable for touch screen SoC applications.Based on a 5 MSBs （most-significant-bits）-plus-5 LSBs （least-significant-bits） C-R hybrid D/A conver sion and low-offset pseudo-differential comparison approach, with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method, an 8-channel 10-bit 200-kS/s SAR ADC （successiveapproximation-register analog-to-digital converter） IP core for a touch screen SoC （system-on-chip） is implemented in a 0.18 μm 1P5M CMOS logic process. Design considerations for the touch screen SAR ADC are included. With a 1.8 V power supply, the DNL （differential non-linearity） and INL （integral non-linearity） of this converter are measured to be about 0.32 LSB and 0.81 LSB respectively. With an input frequency of 91 kHz at 200-kS/s sampling rate, the spurious-free dynamic range and effective-number-of-bits are measured to be 63.2 dB and 9.15 bits respectively, and the power is about 136 μW. This converter occupies an area of about 0.08 mm^2. The design results show that it is very suitable for touch screen SoC applications.

关 键 词：analog-to-digital converter SAR touch screen SoC CMOS integrated circuits low power 

分 类 号：TP334.3[自动化与计算机技术—计算机系统结构]