一种层次式加载BUFFER的时钟网布线  

A Hierarchical Clock Routing with Buffer Insertion

作　　者：李芝燕[1] 潘云鹤[1] 姚丽红[2] 严晓浪[2] 

机构地区：[1]浙江大学计算机系,杭州310027 [2]杭州电子工业学院CAD所,杭州310037

出　　处：《电路与系统学报》1999年第2期23-29,共7页Journal of Circuits and Systems

基　　金：国家"九五"攻关项目资助

摘　　要：多级时钟树构造是解决时钟布线问题的关键。本文提出一种新的层次式布线策略，它将拓扑生成。绕障碍DME及BUFFER定位同时进行考虑，避免了布线的盲目性，减少了后处理工作。首先，对时钟汇点进行层次式均匀划分，在各个局部区域同时进行时钟子树的拓扑生成和DME嵌入：然后，根据各局部区域的布线情况，平衡各子树的负载和延迟，为各区域分配适当驱动能力的BUFFER。算法中的BUFFER定位是层次式的，有利于减少时钟偏差敏感度。实验表明，与将BUFFER插入作为后处理步骤相比，我们的算法在连线总长、延迟方面取得了明显的改善。Multi-stage clock tree construction is a key factor for clock routing. This paper proposes a novel hierarchical clock routing approach. In this approach, optimized topology generation, obstacle-avoiding DME, buffer insertion are taken into consideration simultaneously. First, a hierarchical balanced partition is introduced, then local topology construction and DME are implemented. Afterwards, the load and delay are balanced according to the generated sub-trees, and the suitable buffers are assigned to these sub-trees.The buffer insertion is hierarchically arranged, as to reduce the sensitivity of clock skew. Experimental results show that compared with those post-layout buffer insertion methods, the performance of our algorithm is greatly improved in wire length and delay.

关 键 词：时钟布线 DME嵌入 BUFFER定位 IC CAD 

分 类 号：TN402[电子电信—微电子学与固体电子学] TP391.72[自动化与计算机技术—计算机应用技术]