一种高速连续时间Sigma-Delta ADC设计  

Design of Sigma-Delta ADC with High-speed and Continuous-time

作　　者：张洲洋[1] 王新安[1] 张兴[1] 

机构地区：[1]北京大学深圳信息工程学院集成微系统重点实验室,广东深圳518055

出　　处：《现代电子技术》2010年第20期1-4,共4页Modern Electronics Technique

摘　　要：在TSMC 0.18μm CMOS工艺下设计了一款宽带宽、低功耗的连续时间Sigma-Delta ADC调制器。该调制器可以应用于无线通信、视频、医疗和工业成像等领域,它采用三阶RC积分环路滤波结构,提高了可达到的精度。针对环路延时降低系统稳定性的问题,在环路中引入半个采样周期的延时,以此提高调制器的精度;同时采用非回零的DAC结构来减小系统对时钟抖动的敏感度。通过结构的选取和非回零的DAC结构的使用,调制器对时钟抖动有很强的忍受能力。该Sigma-Delta ADC的带宽可以达到5 MHz,信噪比可达63.6 dB(10位),整个调制器在1.8 V的电压下,功耗仅为32 mW。A wide-bandwidth low-power continuous-time Sigma-Delta ADC modulation, which can be used in wireless communication, video, medicine and so on, is designed with 0.18 μm CMOS process of TSMC. A structure of the 3rd-order RC integration loop filter and a half-time delay are adopted to improve the SNR. The non-return-zero DAC is used to reduce the influence of the system on the sensitivity of the clock jitter. The modulator has a strong tolerance for the clock jitter due to the application of Non-return-zero DAC. The SNR of Sigma-Delta ADC achieves 63. 6 db （10 bit） in the 5 MHz bandwidth. The total power consumption of the modulator is only 32 mW at 1.8 V.

关 键 词：Sigma—Delta A/D转换器 连续时间调制器 高速低功耗ADC调制器 时钟抖动 

分 类 号：TN929.11[电子电信—通信与信息系统]