A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array  

作　　者：CHEN Kai LIU Shubin AN Qi 

机构地区：[1]Key Laboratory of Technologies of Particle Detection ＆ Electronics, Chinese Academy of Sciences, Department of Modern Physics, University of Seience and Technology of China, Hefei 230026, China [2]Anhui Key Laboratory of Physics Electronics, Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China

出　　处：《Nuclear Science and Techniques》2010年第2期123-128,共6页核技术（英文）

基　　金：Supported by National Natural Science Foundation of China (No. 10405023);Knowledge Innovation Program of The Chinese Academy of Sciences (KJCX2-YW-N27)

摘　　要：In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter （TDC） is implemented in an ALTERA＇s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block （LAB） having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity （DNL） is about 0.2 Least Significant Bit （LSB, 165 ps in this TDC module）, and the Integral Nonlinearity （INL） is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.

关 键 词：现场可编程门阵列 时间数字转换器 位时钟 高精度 抽头延迟线 多相 基础 微分非线性 

分 类 号：TN791[电子电信—电路与系统] TL824[核科学技术—核技术及应用]