基于FPGA的实时峰均比抑制算法  

A real-time PAPR reduction algorithm based on FPGA

作　　者：胡茂海[1] 叶江峰[1] 严俊[1] 蒋鸿宇[1] 张伟[1] 

机构地区：[1]中国工程物理研究院电子工程研究所,四川绵阳621900

出　　处：《信息与电子工程》2010年第5期565-568,593,共5页information and electronic engineering

摘　　要：为了克服多载波传输系统具有较高峰均比(PAPR)的固有缺点,介绍了PAPR的定义和目前国内外几种主要降低PAPR的技术。针对现行的PAPR抑制算法复杂度高,实时性差,改变信号频谱分布的缺点,提出了一种基于现场可编程门阵列的实时PAPR抑制算法实现方法。该方法在对原有的PAPR抑制算法进行改进的基础上,根据等效缩比原理,使用XILINX公司的Virtex-5芯片予以实现。实验结果表明,本方法是实时、有效、可行的。Multi-carrier transmission has been employed widely for communications and jamming system.But high Peak to Average Power Ratio（PAPR） of the transmitted signal is a major drawback of multi-carrier transmission system.This paper introduces the definition of PAPR and some main methods of PAPR reduction.In order to reduce the large computation complexity of traditional methods and keep the invariability of spectrum,a real-time PAPR reduction algorithm based on Field Programmable Gate Array（FPGA） has been proposed.This method improves the traditional phasing algorithm and has been implemented in Virtex-5 chip of XILINX.The experiment results show that the proposed method can reduce the PAPR with low complexity,and thus is of good practicability.

关 键 词：现场可编程门阵列 峰均比 等效缩比 

分 类 号：TN919.3[电子电信—通信与信息系统]