Implementation of area optimization precoder in a 40 Gb/s PolDM-DQPSK system  

作　　者：周黎明 张阳安 张明伦 王盖 张锦南 黄永清 李玲 

机构地区：[1]Key Laboratory of Information Photonics and Optical Communications,Beijing University of Posts and Telecommunications,Ministry of Education

出　　处：《Optoelectronics Letters》2010年第6期446-448,共3页光电子快报（英文版）

基　　金：supported by the National High Technology Research and Development Program of China (No.2009AA01Z224);the National 111 Project (No.B07005);the Program for Changjiang Scholars and Innovative Research Team in University of China (No.IRT0609)

摘　　要：In this paper,a new model based on an improved Brent Kung(BK) parallel prefix network(PPN) algorithm is proposed and realized in the field programmable gate array(FPGA).This model is employed in the implementation of 20 Gb/s differential quadrature phase-shift keying(DQPSK) precoder in 40 Gb/s polarization division multiplex(PolDM) DQPSK system.In the computation process,the computation complexity(area) optimization with fan-out limited is achieved.In the implementation,770 FPGA slice registers are utilized,which save about 60% logic resources compared with the previous Kogge Stone(KS) algorithm.In this paper,a new model based on an improved Brent Kung（BK） parallel prefix network（PPN） algorithm is proposed and realized in the field programmable gate array（FPGA）.This model is employed in the implementation of 20 Gb/s differential quadrature phase-shift keying（DQPSK） precoder in 40 Gb/s polarization division multiplex（PolDM） DQPSK system.In the computation process,the computation complexity（area） optimization with fan-out limited is achieved.In the implementation,770 FPGA slice registers are utilized,which save about 60% logic resources compared with the previous Kogge Stone（KS） algorithm.

关 键 词：QPSK系统 GB 优化 编码器 现场可编程门阵列 面积 正交相移键控 FPGA 

分 类 号：TN762[电子电信—电路与系统]