基于FPGA的高速RS译码器设计  

Design of the high speed RS decoder based on FPGA

作　　者：殷爱菡[1] 刘方仁[1] 陈燕燕[1] 

机构地区：[1]华东交通大学信息工程学院,江西南昌330013

出　　处：《电子技术应用》2010年第11期66-68,共3页Application of Electronic Technique

摘　　要：提出了一种基于RiBM算法的RS(255,223)高速译码器设计方案,并采用FPGA和VerilogHDL实现了该译码器。译码器采用三级流水线结构实现,其中关键方程求解模块采用RiBM算法,具有译码速度快、占用硬件资源少等优点。仿真结果验证了该译码器设计方案的有效性和可行性。The design proposal of the RS （255,223） high speed decoder based on RiBM algorithm is put forward, and the decoder is implemented with FPGA and Verilog HDL. The decoder has advantages of high decoding speed and occupancy less hardware resources, which is realized with three-level pipeline structure and the module of key equation solution is implemented with RiBM algorithm. The simulation result validates the validity and feasibility of the design proposal of the decoder.

关 键 词：RS(255 223) FPGA RiBM算法 

分 类 号：TN919[电子电信—通信与信息系统]