片上实时功耗监控与估测的分析设计  

On Chip Run-Time Power-Estimate Analyze and Design

作　　者：段玮[1,2,3,4] 章隆兵[1,2,4] 

机构地区：[1]中国科学院计算机系统结构重点实验室,北京100190 [2]中国科学院计算技术研究所,北京100190 [3]中国科学院研究生院,北京100049 [4]北京龙芯中科技术服务中心有限公司,北京100190

出　　处：《计算机辅助设计与图形学学报》2010年第11期2053-2060,共8页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家"核高基"科技重大专项课题(2009ZX01028-002-003;2009ZX01029-001-003);国家"八六三"高技术研究发展计划(2008AA010901;2009AA01Z125);国家"九七三"重点基础研究发展计划项目(2005CB321600);国家自然科学基金(60736012;60803029;60921002)

摘　　要：为了给操作系统提供实时的芯片热点和功耗统计信息,以便进行快速、准确的实时功耗管理,基于龙芯2号处理器核,提出一个基于门控时钟统计的实时功耗监控系统.通过记录处理器门控时钟的翻转信息来获得芯片热点分布状态,并使用在芯片设计流程中由门级网表仿真而建立的功耗模型进行硬件计算,最终获得向操作系统提供的实时功耗数据.文中提出的实时功耗监控系统具有硬件集成、结构无关、快速、自身开销小、对处理器性能影响小、准确性高等优点.实验结果表明,将该实时功耗监控系统应用在FPGA平台上的功耗估测速度比传统仿真速度提高近40倍,精确度与Synosys公司的EDA工具测量相比可以保持在5%以内.For the purpose of providing the run-time power information to the operating system,and facilitating fast and accurate power management,we propose a run-time power-estimate system which is based on clock gating cells monitoring.This system records the processor＇s clock gating toggle information,and then acquires the hot-spots of the chip,finally,provides the necessary run-time power information to the operating system according to the result which is computed by hardware using a power model.The power model is established through the pre-silicon netlist simulation.This design is hardware integrated,and structure unrelated.It has the advantage of high speed,small overhead,low reduction of processor performance and high accurate.Experimental results on FPGA platform show that this system is faster than traditional simulation by nearly 40 times,and has a small deviation in 5% compared with the result of EDA tools.

关 键 词：处理器 实时 功耗评估 门控时钟 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]